Master in Security of Integrated Systems and Application : Secure your future

Program

Fault Analysis and Counter-Measures (17.5h)

Olivier Benoit and Pascal Manet

Design of secure devices

  1. Introduction to integrated systems (7h)
  2. VHDL design (28h)
  3. VHDL synthesis (14h)
  4. Smart cards and silicon technologies (7h)
  5. Design of a cryptographic module (42h)
  6. Integrated circuits test (17.5h)
  7. Formal verification (17.5h)
  8. Embedded systems development (21h)
  9. Hardware security (7h)
  10. Side-channel analysis and counter-measures (28h)
  11. Fault analysis and counter-measures (17.5h)
  12. Bus security and integrated networks (3.5h)

Synopsis

This course aims at

  • explaining the basic principles of fault attacks;
  • surveying known fault attacks against symmetric crypto-algorithms (DES, AES) and asymmetric crypto-algorithms (RSA);
  • knowing the strenghts and weaknesses of proposed countermeasures;
  • being able to evaluate the resistance of a circuit against faults.

Fault attacks are implemented through a software simulation.

Timetable

(A session amounts to 13/4 hours.)
Session 1
General principles behing fault attacks
Session 2
Fault attacks against DES
Session 3
Fault attacks against AES
Session 4
Countermeasures for DES and AES
Sessions 5–6
Implementation of fault attacks against AES
Session 7
Fault attacks against RSA
Session 8
Countermeasures for RSA
Sessions 9–10
Implementation of fault attacks against RSA

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