Master in Security of Integrated Systems and Application : Secure your future

Program

VHDL Synthesis (14h)

Jacques Rouillard

Design of secure devices

  1. Introduction to integrated systems (7h)
  2. VHDL design (28h)
  3. VHDL synthesis (14h)
  4. Smart cards and silicon technologies (7h)
  5. Design of a cryptographic module (42h)
  6. Integrated circuits test (17.5h)
  7. Formal verification (17.5h)
  8. Embedded systems development (21h)
  9. Hardware security (7h)
  10. Side-channel analysis and counter-measures (28h)
  11. Fault analysis and counter-measures (17.5h)
  12. Bus security and integrated networks (3.5h)

Synopsis

The training gives the basis of synthesis using a high-level language (here VHDL). It assumes as a prerequisite a working knowledge of VHDL, and a good understanding of logic design.

Timetable

(A session amounts to 13/4 hours.)
Session 1
VHDL as a design entry
Session 2
Review of the usable VHDL subset
Sessions 3 and 4
Lab: Logic design
Sessions 5 and 6
Lab: Finite state machines
Sessions 7 and 8
Lab: Blocks, structure

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